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jddes
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Frequency-comb-DPLL
Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya
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GUI is not responding
#16
Bhanuprakash333
opened
2 years ago
0
Detecting "cold boot" situations to force push default values would be very helpful
#15
jddes
opened
3 years ago
0
Can't get actual values
#14
kaikai-liu
opened
4 years ago
4
Console prints a "Loss of synchronization detected" after using the VNA
#13
jddes
opened
4 years ago
0
Update with lastest version
#12
alex123go
closed
5 years ago
0
Add reconnection and loadParameters for third DAC, change KpCrossing …
#11
alex123go
closed
5 years ago
0
debugging adds 6/14
#10
dspen
closed
6 years ago
1
minor fixes, trigger enables lock immediately (no delay)
#9
dspen
closed
6 years ago
0
VNA calibration / Cascade lock correction / kp crossover checkbox behavior / port number selection
#8
alex123go
opened
6 years ago
0
Pr/3
#7
jddes
closed
6 years ago
0
Rectangular Counter Only Reading Every Other New Value
#6
cdfredrick
closed
5 years ago
0
Autorecover
#5
cdfredrick
closed
6 years ago
0
Quick fixes
#4
cdfredrick
closed
7 years ago
0
Dpll python3
#3
alex123go
opened
7 years ago
0
Remove a VCO + add a mux for the remaining one
#2
alex123go
closed
7 years ago
0
FPGA modification - adding mux
#1
alex123go
closed
7 years ago
0