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jhunterh / Cache-Hierarchy-Simulation-Tool

This tool is a highly configurable cache hierarchy simulator for use in computer architecture research and study.
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Look into running SPEC benchmarks #46

Closed CapdinCrando closed 5 months ago

jhunterh commented 5 months ago

execution time is long but the biggest issue is dataset size. Unoptimized code on main produces a dataset size of ~28 GB with SPEC benchmark 657 test dataset. Initial optimization was done by removing pid from each entry. This reduced set size down to ~20 GB. The next optimization is to pipe all output into bzip compression. This drastically reduces set size to ~4-5 GB but at the cost of increased execution time. The next optimization that I will try will be to implement a period parameter similar to what is implemented in the LaCASA mtrace program. http://lacasa.uah.edu/index.php/software-data/mtrace-tools-and-traces

jhunterh commented 5 months ago

Another idea for decreasing trace size is to implement a granularity parameter that reduces the need to have a timestamp (64-bits) associated with each instruction in the trace.