jlpteaching dinocpu issues

jlpteaching / dinocpu

A teaching-focused RISC-V CPU design used at UC Davis

BSD 3-Clause "New" or "Revised" License

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issues

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Improve the single stepper

#112 powerjg closed 4 years ago
0
Update jelf to 0.4.1

#111 jardhu closed 4 years ago
1
build.sbt uses unresolved jelf dependency

#110 jardhu closed 4 years ago
2
Update single stepper to print better

#109 powerjg closed 4 years ago
0
Remove debug statements in the chisel

#108 powerjg closed 4 years ago
0
Add dumpAllInfo function to Tester

#107 powerjg closed 4 years ago
0
Update simulator to use AnnotationSeq instead of options

#106 powerjg opened 4 years ago
1
CSR implementation uses deprecated functions

#105 powerjg opened 4 years ago
0
Update CSR to use reset functions for bundles

#104 powerjg opened 4 years ago
0
Remove dontcares and clean up some style

#103 powerjg closed 4 years ago
1
Convert travis to gh actions

#102 powerjg opened 4 years ago
0
Update the container files

#101 powerjg closed 4 years ago
0
Update to release version of chisel

#100 powerjg closed 4 years ago
2
Update docker and singularity containers

#99 powerjg closed 4 years ago
1
Suppress warnings in test output

#98 jardhu closed 4 years ago
2
Update documentation to reflect new namespace heirarchy

#97 jardhu closed 4 years ago
1
Remove deprecation and warning messages in test output

#96 jardhu opened 4 years ago
0
Split dinocpu namespace into various packages

#95 jardhu closed 4 years ago
0
Move pipeline code to dinocpu.pipelined package

#94 jardhu closed 4 years ago
4
Use Chisel release 3.2.0

#93 powerjg closed 4 years ago
0
Implement a stage register module

#92 jardhu closed 4 years ago
2
Add a pipeline stage register interface and module

#91 jardhu closed 4 years ago
4
Add example single stepping with register

#90 powerjg closed 4 years ago
1
Add special bubble symbol

#89 powerjg opened 5 years ago
0
Go through all conditions and make logical vs bitwise consistent

#88 powerjg closed 4 years ago
0
Add non-combinational CPU model

#87 jardhu opened 5 years ago
12
Create hierarchy in classes

#86 powerjg closed 4 years ago
2
Develop new non combinational CPU model

#85 jardhu closed 5 years ago
1
Fix Treadle output directory bug

#84 jardhu closed 4 years ago
4
Create different InsnTest cases for non-combinational mem + pipelined CPU

#83 jardhu opened 5 years ago
1
Integrate combin memory into pipelined and single-cycle CPUs

#82 jardhu closed 5 years ago
14
Write up memory documentation

#81 jardhu closed 5 years ago
0
Fix DontCares

#80 powerjg closed 4 years ago
1
Minor updates to MemPortIO

#79 powerjg closed 5 years ago
0
Implement combinational modular memory

#78 jardhu closed 5 years ago
2
fixed incomplete code block

#77 nganjehloo closed 5 years ago
0
updated toolchain link, added details for baremetal

#76 nganjehloo closed 5 years ago
0
added more details about printing and verilog

#75 nganjehloo closed 5 years ago
0
Move branch predictor CPU into its own file

#74 powerjg closed 5 years ago
0
Made some minor corrections and additions

#73 nganjehloo closed 5 years ago
0
Dissassembly is supported

#72 nganjehloo closed 5 years ago
0
removed five-cycle cpu

#71 nganjehloo closed 5 years ago
0
removed five-cycle from testing documentation

#70 nganjehloo closed 5 years ago
0
updated cheet sheet link to point to 3.0 version

#69 nganjehloo closed 5 years ago
0
updated history description to be a bit more accurate

#68 nganjehloo closed 5 years ago
0
initial merge b4 rebase. csr can now write to mtvec, added fence as a nop

#67 nganjehloo opened 5 years ago
1
Clean things up for DINO CPU release

#66 powerjg closed 5 years ago
2
Parameterize memory block sizes and modularize specific memory code

#65 jardhu opened 5 years ago
0
Hook disassembler into new REPL interface

#64 powerjg closed 4 years ago
0
Scala grader

#63 DanG100 opened 5 years ago
1

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