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jotego / jtopl

Verilog module compatible with Yamaha OPL chips
GNU General Public License v3.0
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Bad assignments #13

Closed jotego closed 7 months ago

jotego commented 10 months ago

Reported by e-mail. This probably refers to https://github.com/jotego/jtopl/commit/2a44a7f99d2f25e426bf17fc5f36db6e67f73a51

That commit features the single-cycle write on channels. It causes problems in cores so jtcores is using an earlier commit. This issue report might be related to that.

ERROR:Xst:880 - "jtopl_reg_ch.v" line 108: Cannot mix blocking and non blocking assignments on signal . ERROR:Xst:1468 - "jtopl_pg_sum.v" line 39: Unexpected event in always block sensitivity list. ERROR:Xst:902 - "jtopl_eg_final.v" line 41: Unexpected ksl_lut event in always block sensitivity list.

These are minor and are easy to get around... "jtopl_reg_ch.v"... I just remove line 108

"jtopl_pg_sum.v"... I replace the reg by a wire outside the always block wire [21:0] phinc_mul = { 5'b0, phinc_pure} * factor[mul];

"jtopl_eg_final.v"... same, I use a wire instead of reg wire [ 7:0] ksl_base = {1'b0, ksl_lut[fnum]}- { 1'b0, 4'd8-{1'b0,block}, 3'b0 };

jeanh17 commented 10 months ago

These errors were reported by ISE... other synthesis tools might be fine

jotego commented 7 months ago

Modified the phinc_mul and ksl_base assignments for ISE compatibility. I have left line 108 of jtopl_reg_ch.v as it is because removing it causes a warning in Quartus, which is the main tool.