JTOPL FPGA Clone of Yamaha OPL hardware

(c) Jose Tejada. You can show your appreciation by supporting Patreon releases.

JTOPL is an FM sound source written in Verilog, fully compatible with YM3526. This project will most likely grow to include other Yamaha chips of the OPL family.

Using JTOPL in a git project

If you are using JTOPL in a git project, the best way to add it to your project is:

1. Optionally fork JTOPL's repository to your own GitHub account
2. Add it as a submodule to your git project: git submodule add https://github.com/jotego/jtopl.git
3. Now you can refer to the RTL files in jtopl/hdl

The advantages of a using a git submodule are:

1. Your project contains a reference to a commit of the JTOPL repository
2. As long as you do not manually update the JTOPL submodule, it will keep pointing to the same commit
3. Each time you make a commit in your project, it will include a pointer to the JTOPL commit used. So you will always know the JTOPL that worked for you
4. If JTOPL is updated and you want to get the changes, simply update the submodule using git. The new JTOPL commit used will be annotated in your project's next commit. So the history of your project will reflect that change too.
5. JTOPL files will be intact and you will use the files without altering them.

Features

The implementation tries to be as close to original hardware as possible. Low usage of FPGA resources has also been a design goal.

Accuracy

• Follows Y8950 block diagram by Yamaha
• Barrel shift registers used for configuration values
• Takes note of all known reverse engineered information, particularly die shots
• Accurate at sample level, and at internal cycle clock where reasonable
• Original architecture kept as much as possible

Some reference works used:

• NukeYT's Nuked-OPLL
• Research by Andete
• Mitsutaka Okazaki's emu2413

Modern Design for FPGA

• Fully synchronous
• Clock enable input for easy integration
• Avoids bulky multiplexers

Directories:

• hdl -> all relevant RTL files, written in verilog
• ver -> test benches
• ver/verilator -> test bench that can play vgm files

Usage

Although many files are shared, each chip has its own top level file to instantiate. There are YAML files for each one that detail the list of files used for each file. These files can be easily converted to whatever format you need, like .qip.

Not all the chips of OPL series are implemented yet, so take the following table as a plan which I am working on.

Chip differences

Simulation

There are several simulation test benches in the ver folder. The most important one is in the ver/verilator folder. The simulation script is called with the shell script go in the same folder. The script will compile the file test.cpp together with other files and the design and will simulate the tune specificied with the -f command. It can read vgm tunes and generate .wav output of them.

Tested Features

Each feature is tested with a given .jtt file in the ver/verilator/tests folder.

Note* values don't match the app notes but implementation follows reverse engineering of OPLL and OPL3. Measuring from first note of an octave to last note of the next seems to fit better the table in the notes.

Rhythm Instruments

They are bass drum, snare drum, tom-tom, high-hat, cymbals and top cymbals. Channels 6,7 and 8 are used for these instruments.

For patch-based OPL chips, there were specific values for each operator register of these instruments. However, for non-patched synthesizers, the user still had to enter register values. So it looks like the benefit from the rhythm feature was:

• Ability to enter more than one key-on command at once
• Noisy phase for three instruments
• Forced no modulation on 5 five instruments

Related Projects

Other sound chips from the same author (Verilog RTL)

Cycle accurate FM chips from Nuked (software emulation)