Fix timer irq activation 1 period earlier

jotego / jtopl

Verilog module compatible with Yamaha OPL chips

GNU General Public License v3.0

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Fix timer irq activation 1 period earlier #5

Closed gyurco closed 2 years ago

gyurco commented 2 years ago

Fixes: #4

jotego commented 2 years ago

I haven't had the time to simulate your comments in #4 or this commit. So I am going to take your word for it and merge it. The fact that part of the counter is free running seems to be a constant across Yamaha designs and it actually makes sense because it lets the CPU reload the counter without breaking the period. If the CPU reloaded all bits, the interrupt interval would have some variability.

gyurco commented 2 years ago

In this commit I didn't touch the flagen bits, only the off-by-one error of the timer overflow. On a PC (Adlib or Soundblaster cards) the timer seems to be used only for card detection, as the IRQ line is not connected to the ISA bus, and the PC has a timer chip anyway.