[Assignment 3] M extension (due: 11/10, 23:59:59 (KST))

[minseongg]

Implement the M extension.

• Read the description here.
• You're going to modify riscv_isa.rs and exe.rs.
• Make a submission file with bash scripts/make_submission.sh and then submit hw3.zip to here.
• We recommend you starting this assignment after understanding how the baseline CPU implementation works.
  • Please refer to the User Guide. (WIP, we will finish it ASAP)
  • It will be covered in the "Pipelined RISC Processor" section in the lecture.
• IMPORTANT: Only the last submission will be used for grading. Please make sure the last submission passes the testbench.
• IMPORTANT: Don't fork the hazardflow repository, It'll be public!

[minseongg]

IMPORTANT: We updated the skeleton code for CPU, please download changes in the upstream.

Changes:

• Removed Zifencei ISA from baseline CPU
• Implemented CSR with combinators
• Refactored and simplified the implementation