kaist-cp / cs492-uarch

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KAIST CS492: Microarchitecture Design

Logistics

Course Description

Context

It is "A Golden Age for Computer Architecture", and also "A Golden Age of Hardware Description Languages". The demand for a tremendous amount of computation necessitates the development of purpose-built, specialized hardware (also known as accelerators), and consequently, productive RTL design tools (such as hardware description languages or HDLs) for these accelerators.

Goal

In this course, you will learn an opinionated RTL design process, specifically using "HazardFlow HDL", developed at the KAIST Concurrency and Parallelism Laboratory. HazardFlow HDL facilitates modular RTL design of pipelines even in the presence of hazards. Unlike existing high-level HDL and high-level synthesis tools for similar purposes, HazardFlow HDL aims to provide predictable performance, power, and area (PPA) transparently to designers. By understanding and developing designs in HazardFlow HDL, students are expected to build a modern and effective perspective on RTL designs.

Textbook

Prerequisites

Schedule

Tools

Ensure you are proficient with the following development tools:

Grading & Honor Code

Cheating

IMPORTANT: READ CAREFULLY. THIS IS A SERIOUS MATTER.

Programming Assignments (80%)

Final Exam (20%)

Attendance (?%)

Communication

Registration

Rules

Ignore

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