registerFile.sv

[rajugupta95]

1) assign read_data1 = (read_reg1==6'd0) ? {1'b0, 32'd0} : {busy[read_reg1], rf[read_reg1]}; //Is read_data1 and read_data2 32bit or 33bit wide?? 2) Is busy signal a 1bit or 64 bitwide??

[kivantium]

1. read_data1 is declared as output logic [32:0] read_data1, read_data2;, so it is 33 bit wide.
2. busy is declared as logic [63:0] busy;, so it is 64 bit wide. Each bit is used for each register. We have 64 registers, so we need 64 busy signals.