Open Johnlon opened 4 years ago
also it would be interesting to invoke command to simulate dumped probes in a testbench, like executing GtkWave (included in Win32 version of IVerilog) with a VCD file generated from vvp stage, and to do possible compile multiple source files, like tesbench, included in the same workspace
j054n I just realised I can just edit the plugin on my own file system as the whole thing is just two plain text files. Perhaps you could add this feature with a bit og vsconfig code?
@leafvmaple This issue would be handled by #11
@bit-wrangler check my fork, it is on VSCode Marketplace, it has this feature as well as other features. https://github.com/MohammadKurjieh/vscode-verilog
I want to be able to pass 'iverilog -Ttyp -Wall -g2012 -gspecify' when running iverilog
How do I for instance turn on system verlilog support without this?