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lowRISC / sonata-system

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
Apache License 2.0
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Add SPI test for CHERI #200

Closed AlexJones0 closed 1 week ago

AlexJones0 commented 1 week ago

This PR adds a SPI test to the existing baremetal CHERI test runner. For now, this is a simple smoketest that simply tests a few commands for the SPI flash - other SPI connections are not included.

The SPI tests consist of 3 components:

  1. Read the JEDEC ID from flash over SPI and check it matches the value we expect.
  2. Erase 1 random sector (4 KiB) from flash over SPI, and check that the entire sector was properly erased.
  3. Write 10 random pages (256 B) to flash over SPI, and then read back the data to check that it matches what was written.

The number of test iterations and the number of sectors and pages can each be configured via compilation flags. These numbers are purposefully kept fairly low to keep runtime reasonable on Verilator.

This commit also includes minor changes to the flash-utils.hh simple SPI driver, to allow it to use 4-byte addresses required for testing the entirety of the flash via SPI.

This has been tested on both FPGA and in Verilator, and has also been confirmed to pass 100 iterations with 10 sector erases and 50 page writes each for consistency on FPGA.

AlexJones0 commented 1 week ago

After seeing the issues in flash-utils.hh found by #201, I've made the tests slightly more rigorous so that they ensure that writes/reads are actually happening and not just passing because of deterministic PRNG over test iterations. I've also added an additional fourth test that slows down the SPI clock 8 times and tests writing random data to a random page, to try and catch the issue described there. As suggested in that PR, this new fourth test does indeed fail at the moment as you would expect. All three other tests still pass consistently, as previously described.

AlexJones0 commented 1 week ago

I've also now introduced a commit based on PR #201 that fixes the failing slow SPI clock speed test now. Unlike that PR, this retains the CS falling/rising edges so that instructions are properly executed, and it uses appropriate wait_idle calls to ensure that relevant FIFOs are empty before the CS is modified. I've verified that now with that commit, all four SPI tests pass on both the Verilator and FPGA environment as described before. If this is merged, this closes that PR.