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lowRISC / sonata-system

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
Apache License 2.0
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Do not modify CS whilst SPI controller is active #201

Closed alees24 closed 1 month ago

alees24 commented 2 months ago

Ensure that CS is not changed whilst the SPI controller is active, e.g. after a write into the FIFO that has not necessarily completed on the SPI bus. It is safe to deassert the CS line when a read operation has completed because that necessarily blocks until completion.

The code worked in practice by dint of the CPU writes into the FIFO being slow enough that the SPI at 15Mbps can mostly keep up. If the SPI is slowed to eg. 30/8Mbps then the code sw/cheri/checks/spi_test produced incorrect results in Verilator simulation because the spidpi model responds to the changes on the CS line.

Such issues with the CS line-driving may exist elsewhere in the codebase and particularly for other SPI devices.

HU90m commented 1 month ago

Closing issue should be fixed by the added wait_idles in https://github.com/lowRISC/sonata-system/pull/200