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lowRISC / sonata-system

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
Apache License 2.0
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SRAM address aliasing when HyperRAM is enabled #228

Open djlowther opened 1 month ago

djlowther commented 1 month ago

When HyperRAM is enabled, the the SRAM address bus is only 17 bits wide but ADDR_MASK_SRAM is still 32'h 0003ffff, leading to reads from/writes to addresses 0x00120000-0x0013ffff being accepted but accessing the same physical memory as 0x00100000-0x0011ffff.

marnovandermaas commented 1 month ago

Yes, we need to change the size of the SRAM to 0x00020000 when HyperRAM is disabled here: https://github.com/lowRISC/sonata-system/blob/e73c4574b44dfaabbf57d2418beb3e1fca86e240/data/xbar_main.hjson#L38 We probably need to remove the automatically generated files and get them to be generated by FuseSoC based on the DisableHyperRam flag: https://github.com/lowRISC/sonata-system/blob/e73c4574b44dfaabbf57d2418beb3e1fca86e240/sonata.core#L87