[rtl] Add new SPI IP

[GregAC]

For visibility only, this isn't yet ready for review/merge

I've only tested transmit so far, I've got a slightly hacky integration with ibex-demo-system that demonstrates this SPI block working with the LCD up to 25 MHz.

Outdated, see below.

[GregAC]

Ok this is now good to go. I've tested it against the flash and demonstrated successful write and read back @ 25 MHz. Have yet to try it against the LCD with this iteration though did try the earlier version of the spi_core with a hacked up bus adapter with Ibex demo system and that worked with the LCD.

Note that interrupts are specified but not yet implemented.

I do have some example code though we need a sensible setup for it to work with so it can be included in the repository. Locally I disabled CHERI and just ran it as plain rv32e code. I'm thinking of creating some 'CHERIoT bare' software stub that will jump into a C main function with broad capabilities available so you can write little test programs without worrying about the RTOS or capabilities.

[GregAC]

I'm thinking of creating some 'CHERIoT bare' software stub that will jump into a C main function with broad capabilities available so you can write little test programs without worrying about the RTOS or capabilities.

Ah looks like we've already got more or less what I was thinking of: https://github.com/lowRISC/sonata-system/tree/main/sw/cpp/cheri_sanity

I'll do an SPI flash test using that framework.

[GregAC]

Unfortunately the SPI flash test program isn't yet working on the board though looked ok in sim. Might be something to do with the program load via debug, I haven't tried it as initial SRAM contents.

My original C code that I ported is here: https://gist.github.com/GregAC/b4bdd5ec5d325f96cef2764c0d47b001 (that's intended to run on vanilla Ibex). That was working fine.

[marnovandermaas]

I ran the test program in CHERI mode and got the JEDEC as 0xef4019 which corresponds to the data sheet table in section 8.1.1: https://www.mouser.co.uk/datasheet/2/949/w25q256jv_spi_revg_08032017-1489574.pdf for part W25Q256JVEIQ. However the flash contents read out is all zeros.

I'm now going to check the non-cheri version.

[marnovandermaas]

I added a commit that adds software in the non-CHERI domain and it also reads out zeroes.

[marnovandermaas]

I've updated the LCD demo in the non-CHERI world. It turns on the display but currently does not write anything to it. Still investigating why this is.

[marnovandermaas]

I found the issue, which was that appspi_cs was spelt as appsci_cs in top_sonata.sv as it was passed in through gp_o. Now the non-CHERI flash test passes in FPGA.