Closed alees24 closed 2 months ago
I tested this on FPGA by tying cheri_en
to zero and set the SRAMInitFile
to the location of i2c_hat_id.vmem
. Then I see the following UART output:
i2c_hat_id demo application
clk_period: 40
thigh: 100
tlow: 126
t_f: 1
t_r: 3
thd_sta: 100
tsu_sta: 118
thd_dat: 125
tsu_dat: 7
t_buf: 119
tsu_sto: 100
00000000 : 52 2D 50 69 01 00 03 00 F0 03 00 00 01 00 00 00 : R-Pi............
00000010 : 2D 00 00 00 E7 58 D1 95 F1 56 28 AB CB 4E 99 42 : -....X...V(..N.B
00000020 : C7 79 D6 A3 01 00 01 00 0C 09 52 61 73 70 62 65 : .y........Raspbe
00000030 : 72 72 79 20 50 69 53 65 6E 73 65 20 48 41 54 7F : rry PiSense HAT.
00000040 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
00000050 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
00000060 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
00000070 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : ................
EXCEPTION!!!
============
MEPC: 0x00101222
MCAUSE: 0x00000007
MTVAL: 0x00020008
This PR integrates the I2C block from the OpenTitan project, and updates the software accordingly:
Please note that this demo will not run properly in Verilator simulation because there is presently no I2C DPI model to act as the target device, but may be run on Sonata FPGA by tying the 'cheri_en' low in sonata_system.sv. This code is intended not just to test the operation of the integrated block but also to serve as a guide for CHERIoT driver/application development.