This PR builds on #47, adding the USB device from the OpenTitan project in a similar manner to the integration of the I2C block.
Instantiate usbdev with vendoring and patching (again, please check; this is unfamiliar)
Clock generation is modified to provide a 48MHz clock alongside the - now parameterized - system clock; it is likely that the system clock will be changed at some point, and the initial hope was that the Ibex core could run faster than the present 50MHz.
usbdev requires a 48MHz clock (this is 4 x oversampling of a 12Mbps signal)
usbdev does not have an assigned base so I've just slotted this into the address window of the I2C devices presently; each of these IP blocks requires only a 4KiB window individually.
Simplified code for responding to the configuration messages/set up that the USB host performs is included in sw/c/common/usbdev.c/h. This should suffice for most USB device implementations, but it is deliberately kept quite minimal; derived from the OT code, and intended as 'proof of life'/basis for further software development.
A demo application called 'hello_usb' that mimics the behavior of 'hello_world' is introduced; this will print a sign-on message over the UART and then send a message 'Hello USB! Input value: ' over the a 'simpleserial' USB connection to the USB host, reporting the state of the switches as per 'hello_world.'
The demo application will start up in Verilator simulation but will never receive the configuration Control Transfers at present because there is no integration of the USBDPI model. With Sonata FPGA, once the 'cheri_en' signal is tied low and the appropriate software image specified (sw/c/build/demo/hello_usb/hello_usb.vmem), the application will run on FPGA and the USB output can be observed using 'screen /dev/ttyUSB' where the particular tty assigned may be ascertained from the reports of USB activity in 'dmesg' output.
Any required changes to the I2C vendoring/patching (or anything else) I shall mirror here; please review that first.
This PR builds on #47, adding the USB device from the OpenTitan project in a similar manner to the integration of the I2C block.
The demo application will start up in Verilator simulation but will never receive the configuration Control Transfers at present because there is no integration of the USBDPI model. With Sonata FPGA, once the 'cheri_en' signal is tied low and the appropriate software image specified (sw/c/build/demo/hello_usb/hello_usb.vmem), the application will run on FPGA and the USB output can be observed using 'screen /dev/ttyUSB' where the particular tty assigned may be ascertained from the reports of USB activity in 'dmesg' output.
Any required changes to the I2C vendoring/patching (or anything else) I shall mirror here; please review that first.