Closed HU90m closed 4 months ago
An initial thought, the bus in the Verilator simulation is the same as in the FPGA so that is unlikely the problem.
CC @alees24
It looks like this issue has been resolved in the latest version of the main branch. In conjunction with the following fix: https://github.com/lowRISC/sonata-system/pull/61 Hugo can provide more details but I'm closing this for now.
It looks like this issue has been resolved in the latest version of the main branch. In conjunction with the following fix: #61 Hugo can provide more details but I'm closing this for now.
I have no idea what fixed this problem; a lot has changed in the repository since the last rebase. I'd like to get CI running on this soon-ish, so we can catch it if it does happen to pop up again.
This little fella popped up again.
loader: Error handler for compartment is -1
loader: Error handler for compartment is 216
loader: First pass to find sealing key imports
loader: Creating sealing key 0x10
../sdk/core/loader/types.h:956 Invariant failure in size
Unused bits in sizeAndPermissions are not zero, field contains 0xc4000000
pushd tests
xmake f --board=sonata --debug-scheduler=y --debug-locks=y --debug-cxxrt=y --debug-loader=y --debug-token_library=y
xmake
Loaded onto the FPGA with the sonata system's ./util/mem_helper.sh
.
I traced the re-emergance was actually a different issue. I traced it back to the RTOS not being able to handle very large MMIO regions.
Good work Hugo!
When running the CHERIoT RTOS, I'm hitting an error that looks to be a bug in the hardware.
A global constant is being read back as the wrong value when running on FPGA.
The CHERIoT RTOS build:
The image is found at
build/cheriot/cheriot/release/hello_world
.The tail of the UART log when running on the FPGA:
This field value should be
0xc0001000
and it is in the ELF file, if you look at the contents of section scheduler_code (address0x100f90
). But for some reason at run time it is a different value, even when checked right at the beginning of theloader_entry_point
.When running the same image on the Verilator simulator, this value is correct and the simulation continues past it, which is rather odd.
My best guess at the moment is that there is something wrong the bus or SRAM access.
The simulator fails after this point for a different reason, which I haven't investigated:
You may want to use https://github.com/lowRISC/sonata-system/pull/53 when running longer simulations.