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lowRISC / sonata-system

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
Apache License 2.0
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TL-UL: bus watchdog #7

Open marnovandermaas opened 10 months ago

marnovandermaas commented 10 months ago

Will there be some kind of bus watchdog to catch invalid accesses or lock ups (missing 'heart beat' signal)? I think this is an important development aid, but it could also be configured to restart the system in the event of a violation being caught and reported by CHERI... rather than just leaving the demo 'IoT system' in a dead state.

Question from @alees24 copied from: https://github.com/lowRISC/sonata-system/pull/1#issuecomment-1830495233

marnovandermaas commented 9 months ago

Similar question applies to the instruction side: https://github.com/lowRISC/sonata-system/pull/14#discussion_r1455914251

At the moment, the logic requires tl_main_pkg::ADDR_MASK_SRAM to be a power of two, it would be good to make it work without that assumption.