256KiB RAM, 30MHz system clock on A50T

lowRISC / sonata-system

A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI

Apache License 2.0

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256KiB RAM, 30MHz system clock on A50T #72

Closed alees24 closed 1 month ago

alees24 commented 1 month ago

Increase SRAM size to 256KiB by avoiding bit-level write enables.
Increase system clock frequency to 30MHz (just misses timing at 33MHz presently).
Resurrect legacy 'hello_word' demo application now that rv_timer is usable.

This build is timing clean on A50T and passes legacy code tests (memory_test, i2c_hat_id, hello_world, hello_usb) and hello_compartment from the CHERIoT RTOS world.