issues
search
lsils
/
mockturtle
C++ logic network library
MIT License
210
stars
139
forks
source link
Several I/O-related updates
#506
Closed
lee30sonia
closed
2 years ago
lee30sonia
commented
2 years ago
Update
lorina
- now supports reading Verilog module instantiation in non-topological order
Update
bill
Update
verilog_reader
and
write_verilog
Make it work to write buffered networks with names
lorina
- now supports reading Verilog module instantiation in non-topological orderbill
verilog_reader
andwrite_verilog