lsils / mockturtle

C++ logic network library
MIT License
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Convert a behavioural level verilog file to MIG network #621

Closed Maya7991 closed 10 months ago

Maya7991 commented 10 months ago

Describe the bug While trying to convert a behavioral level verilog to MIG network using the gates_to_nodes(NtkDest) function, I am getting a compilation error that the destination network(MIG network) does not have create_node method `

To Reproduce Steps to reproduce the behavior:

  1. Using mockturtle latest version
using namespace mockturtle;

int main()
{
    std::string input_file, output_file;
    std::cout << "Enter the input file name: "; // filename.v
    std::cin >> input_file;
    std::cout << "Enter a name for output file: "; //output.v
    std::cin >> output_file;

    mig_network gate_network; 

    if ( lorina::read_verilog( input_file, verilog_reader( gate_network )) != lorina::return_code::success )
    {
      fmt::print( "[e] Could not read input file `{}`\n", input_file );
      return -1;
    }

    mig_network mig = gates_to_nodes<mig_network>(gate_network);
    mig = cleanup_dangling(mig);
    write_verilog(mig, output_file);

    return 0;
}
  1. The input Verilog file that has to be converted to MIG.

    
    module half_adder(sum, carry_out, a, b);
    
    input a, b;
    output sum, carry_out;
    
    assign carry_out = a & b;
    assign sum = a ^b;

endmodule


5. Getting the following error message when compiling the main.cpp

/home/vboxuser/DFKI/migConverter/lib/mockturtle/include/mockturtle/algorithms/gates_to_nodes.hpp:86:18: error: static assertion failed: NtkDest does not implement the create_node method 86 | static_assert( has_create_node_v, "NtkDest does not implement the create_node method" ); | ^~~~~~ /home/vboxuser/DFKI/migConverter/lib/mockturtle/include/mockturtle/algorithms/gates_to_nodes.hpp:86:18: note: ‘mockturtle::has_create_node_v’ evaluates to false



**Environment**
 - OS:  Linux
 - Compiler: GCC 11.4.0

The task is to convert a behavioral level Verilog file into an MIG network and write the output to a Verilog file. Please help me know if this task is possible via mockturtle library. If possible, Am I using the correct functions for this task.

It would be very helpful if you can provide some suggestions and help me know if this is the correct way.