Convert behavioral level Verilog file to MIG network

[Maya7991]

The output file is empty when trying to convert behavioral level Verilog file to MIG network

To Reproduce Steps to reproduce the behavior:

1. Using mockturtle latest version

2. 
   using namespace mockturtle;

int main() { std::string input_file, output_file; std::cout << "Enter the input file name: "; // filename.v std::cin >> input_file; std::cout << "Enter a name for output file: "; //output.v std::cin >> output_file;

klut_network gate_network;

if ( lorina::read_verilog( input_file, verilog_reader( gate_network )) != lorina::return_code::success )
{
  fmt::print( "[e] Could not read input file `{}`\n", input_file );
  return -1;
}

klut_network klut = gates_to_nodes<klut_network>(gate_network);

mig_network mig;
convert_klut_to_graph<mig_network>( mig, klut );

mig_network mig1 = cleanup_dangling(mig);
write_verilog(mig1, output_file);
return 0;

}

3. The input Verilog file that has to be converted to MIG.

module half_adder(sum, carry_out, a, b);

input a, b; output sum, carry_out;

assign carry_out = a & b; assign sum = a ^b;

endmodule

4.The output Verilog file should have the MIG network but I am seeing empty output file as shown below:

module top( ); input ; output ; endmodule

**Environment**
 - OS:  Linux
 - Compiler: GCC 11.4.0
 - Compilation mode: RELEASE

My task is to read a verilog file with behavioral level description, convert it to MIG network and write it to an output verilog file. But the output Verilog file is displaying as empty. Please help me understand the issue in the code.

**Check list**
 * [x] I have tried to run in DEBUG mode and there was no assertion failure (or the reported bug is an assertion failure).
 * [x] I have made sure that the provided code compiles and the testcase reproduces the error.
 * [ ] I have minimized the testcase.

[lee30sonia]

Please either provide the top module name as the second argument to the constructor of verilog_reader, or change the module name in the verilog file to "top".

[Maya7991]

Thank you so much for the solution:)