Closed HackHerz closed 1 year ago
I believe the native AIGER writer (io/write_aiger.hpp
) writes out names if the given network is wrapped with names_view
. Read/write Verilog should also work with names.
Please let us know if there is still a problem. It would be helpful to give us your code to locate the problem more easily.
I was wondering if there is a writer that makes use of the names in
names_view
? There seems to be a parser for aiger files that can read intonames_view
(#430) , but i haven't found a suitable writer yet.I simply want to store and load my network between runs of a program, did I overlook an implementation or is there simply none yet? Thanks in advance.