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m-labs / misoc

The original high performance and small footprint system-on-chip based on Migen™
https://m-labs.hk
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different clocking of differentiator and integrator #102

Closed nkrackow closed 3 years ago

nkrackow commented 3 years ago

https://github.com/m-labs/misoc/blob/169dd32c42022140e541af0954be473e715785b9/misoc/cores/cic.py#L32-L35 Idea: The cic is only stable when the integrators are exactly compensated by the differentiators. If there would be a stall of the input data the cic would go unstable here bc the integrators keep on going. But this might not be a problem as you "clock" all your filters from the output backwards so this situation can never occur right?

nkrackow commented 3 years ago

@jordens

jordens commented 3 years ago

Yes. The idea is that this will only work if the rates are steady. Let's show that they are or aren't.

Proper simultaneous output and input handshaking seemed tricky. Certainly if you want to consider situations where you are actually draining and refilling the pipeline.

jordens commented 3 years ago

Not an issue. It's stated in the docstring that the rates need to be maintained externally.