liteeth: Fix Kintex UltraScale GTH intermittent breakage

[HarryMakes]

Fingers crossed, this PR should finally, once and for all, fix https://github.com/m-labs/artiq/issues/1424 where the Ethernet on the KU FPGA on Metlino would randomly break. The symptom can be any of the following:

• After replacing a working FPGA bitstream with another that only differs slightly (e.g. changing the ARTIQ version string in ROM, removing some unused EEM ports from the code), the new bitstream would cause the Ethernet to fail.
• After re-flashing with a new bitstream and reloading it to the FPGA, the Ethernet fails; after power-cycling, the Ethernet resumes to normal.
• After re-flashing with a new bitstream and reloading it to the FPGA, the Ethernet works normal; after power-cycling, the Ethernet fails.
• The Ethernet would randomly fail after each reloading (e.g. by artiq_flash start).

After consulting this Xilinx page, I believe the GTH is still missing some Xilinx parameters or signals, so I tweaked liteeth_mini's current usage of the GTH and tested. At the time of writing, I only needed to add the PROGDIVRESET signal such that both the GTH TX/RX and their programmable divisors are reset altogether, which should guarantee that the TX/RXOUTCLK aren't flatlined. And this has so far eliminated all the symptoms I described above.

It would be best to double check my logic and/or find more symptoms to test with, but I think this PR should be good enough. This has been tested on different units of Metlino, one in Hong Kong (M-Labs) and one in Poland (Creotech).

[sbourdeauducq]

Great! Should a similar fix be applied to https://github.com/m-labs/artiq/blob/master/artiq/gateware/drtio/transceiver/gth_ultrascale.py ?

[jbqubit]

Great find @HarryMakes. Thank you for persevering!