This PR changes the VecRiscv core to VecRiscv_IMA.v in VexRiscv-verilog master to support atomic instructions (lr/sc & amo). (See this PR in VexRiscv-verilog.)
Detail changes
The vexriscv/verilog submodule is updated to include this PR.
vexriscv/core.py now uses VexRiscv_IMA.v.
Updated Machine IRQ Mask register and Machine IRQ Pending register defined in csr-def.h.
Updated cache flushing instruction to fence.i and a custom instruction .word(0x500F).
Testing
BIOS can be built and run using the updated VexRiscv core.
Summary
This PR changes the VecRiscv core to
VecRiscv_IMA.vinVexRiscv-verilogmaster to support atomic instructions (lr/sc&amo). (See this PR inVexRiscv-verilog.)Detail changes
vexriscv/verilogsubmodule is updated to include this PR.vexriscv/core.pynow usesVexRiscv_IMA.v.csr-def.h.fence.iand a custom instruction.word(0x500F).Testing
BIOS can be built and run using the updated VexRiscv core.