Closed occheung closed 2 years ago
Updated the VexRiscv core by bumping the VexRiscv-verilog submodule. For the changes, see the corresponding PR in VexRiscv-verilog.
VexRiscv-verilog
Summary
Updated the VexRiscv core by bumping the
VexRiscv-verilogsubmodule. For the changes, see the corresponding PR inVexRiscv-verilog.