This patch allows the use of VexRiscv CPU that supports 64-bits bus and with a FPU (optional).
Gateware
~~VexRiscv automatically selects the 64-bits variant (VexRiscv_IMA_wide or VexRiscv_G) if the building platform is NOT Kasli v1.x.
Timing issues were observed when using such CPU variants on ARTIQ. Only the original VexRiscv_IMA is supported for these platforms.~~
RV32IMA (VexRiscv_IMA) and the 64-bits bus width version (VexRiscv_IMA_wide), as well as RV32G (VexRiscv_G) are supported.
An additional argument (with_fpuvariant) is added to the VexRiscv target to select the variant.
Name the wishbone interface instance to CPU according to the CPU variant selected. This is to avoid confusion when building with multiple VexRiscv variants.
Software generation
Added riscv32gvexriscv-g CPU type, which supports floating point instructions. (TODO: Cannot build with riscv32g CPU alone at the moment.)
Allow software packages to be built with a different CPU type.
It is to support the usage of a FPU on ARTIQ kernel only. Libraries linked to the kernel needs to be built with the rv32g architecture. Examples in the next point.
Generate libunwind-elf.a``libunwind-riscv32g-elf.alibunwind-vexriscv-g-elf.a only when building libunwind with riscv32gvexriscv-g.
ARTIQ kernel will support floating point instruction. However, the comm CPU will not. In this case, libunwind will need to be added to the software packages as such:
builder.software_packages = []
builder.add_software_package("libunwind", cpu_type=vexriscv-g) # kernel CPU type
# build all the kernel libraries here, see note
builder.add_software_package("libunwind", cpu_type=vexriscv) # comm CPU type
# build the rest
(Note/TODO: The second build of libunwind will wipe out the original libunwind-elf.a built with floating point insn.)
In this case, libunwind-bare.a, libunwind-vexriscv-elf.a and libunwind-riscv32g-elf.alibunwind-vexriscv-g-elf.a are generated. Only libunwind-vexriscv-elf.a is not linked to other libraries.
Summary
This patch allows the use of VexRiscv CPU that supports 64-bits bus and with a FPU (optional).
Gateware
VexRiscv_IMA_wideorVexRiscv_G) if the building platform is NOT Kasli v1.x. Timing issues were observed when using such CPU variants on ARTIQ. Only the originalVexRiscv_IMAis supported for these platforms.~~VexRiscv_IMA) and the 64-bits bus width version (VexRiscv_IMA_wide), as well as RV32G (VexRiscv_G) are supported.with_fpuvariant) is added to theVexRiscvtarget to select the variant.Software generation
riscv32gvexriscv-gCPU type, which supports floating point instructions.(TODO: Cannot build withriscv32gCPU alone at the moment.)rv32garchitecture. Examples in the next point.libunwind-elf.a``libunwind-riscv32g-elf.alibunwind-vexriscv-g-elf.aonly when buildinglibunwindwithriscv32gvexriscv-g. ARTIQ kernel will support floating point instruction. However, the comm CPU will not. In this case,libunwindwill need to be added to the software packages as such:(Note/TODO: The second build of libunwind will wipe out the originalIn this case,libunwind-elf.abuilt with floating point insn.)libunwind-bare.a,libunwind-vexriscv-elf.aandlibunwind-riscv32g-elf.alibunwind-vexriscv-g-elf.aare generated. Onlylibunwind-vexriscv-elf.ais not linked to other libraries.TODOsUpdate dependencies after PR in VexRiscv-verilogTODOs above