As discussed in https://git.m-labs.hk/M-Labs/artiq-zynq/pulls/176 - to prevent AXI bursts from being issued on CSR for Zynq-based systems, this adds dmb() calls for between memory accesses for registers bigger than 32 bits.
This patch adds this feature without breaking compatibility.
Unfortunately this needs to rely on libcortex_a9 - cannot just call llvm_asm as that requires corresponding feature enabled in the crate (not file).
Few things come to mind now - since it's limited to only one platform, maybe CPU type should be also passed? Or the argument could be called use_cortexa9_dmb instead?
sbourdeauducq
commented
2 years ago
As discussed in https://git.m-labs.hk/M-Labs/artiq-zynq/pulls/176 - to prevent AXI bursts from being issued on CSR for Zynq-based systems, this adds
dmb()calls for between memory accesses for registers bigger than 32 bits.This patch adds this feature without breaking compatibility.
Unfortunately this needs to rely on
libcortex_a9- cannot just callllvm_asmas that requires corresponding feature enabled in the crate (not file).Few things come to mind now - since it's limited to only one platform, maybe CPU type should be also passed? Or the argument could be called
use_cortexa9_dmbinstead?