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m-labs / misoc

The original high performance and small footprint system-on-chip based on Migen™
https://m-labs.hk
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Remove litescope references from UART #13

Closed sbourdeauducq closed 9 years ago

sbourdeauducq commented 9 years ago

And do not call the WB bridge "frontend".

enjoy-digital commented 9 years ago

I've tried to change this, hope it's better.

sbourdeauducq commented 9 years ago

I don't think the name uart.wishbone is relevant. Those names should reflect the role that the UART has, either as a target device that receives the characters to write from a CPU through a bus (Wishbone, CSR, ...), or as an initiator device that masters a bus.

sbourdeauducq commented 9 years ago

Maybe uart.UART for the normal CSR target peripheral (since this is the most common, default, assumed role of a UART in a SoC), and uart.bridge.Wishbone for the initiator/bridge.

enjoy-digital commented 9 years ago

Thanks, so is it OK if I rename wishbone.py in bridge.py ? (I want to avoid creating a bridge directory for now since we only have a wishbone bridge, eventually later if we have others bridges (AXI, Avalon))

sbourdeauducq commented 9 years ago

Sounds good.

enjoy-digital commented 9 years ago

Done, thanks for the feedback!

sbourdeauducq commented 9 years ago

Thanks for fixing it!