To allow more flexibility in configuration, mostly necessary for DRTIO, few changes were made:
si5324 output is not chosen by default anymore - need to specify the "main" clock signal - so txoutclk can be passed, or in future wrpll or other sources,
div2 parameter was added, in case the "main" clock signal is not 62.5MHz but full speed,
full-speed 125MHz bootstrap clock is generated by the same PLL that generates 200MHz for IDELAYCTRL,
clock switch can be triggered by any signal, and if none is provided, CSR is still created to be used by software - so it can be triggered by tx_init.done, simplifying slightly the sequence of clock setup in software for DRTIO.
To allow more flexibility in configuration, mostly necessary for DRTIO, few changes were made:
txoutclkcan be passed, or in future wrpll or other sources,IDELAYCTRL,tx_init.done, simplifying slightly the sequence of clock setup in software for DRTIO.