Closed olofk closed 9 years ago
Thanks for patch. As we discussed, this is more an issue with the verilog Migen generates than something that has to be changed in the code. For now you can use my Migen fork to solve that: https://github.com/enjoy-digital/migen I'll try to fix that in upstream Migen.
Some simulators, notably Vivado's XSIM endlessly relaunches combinatorial processes that read and write the same register.
This patch avoids that problem by only reading from registers that are not written to in the same process. The replaced registers are equivalent, so no logical changes are introduced