UART: Evaluate irq conditions and choose the best

m-labs / misoc

The original high performance and small footprint system-on-chip based on Migen™

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UART: Evaluate irq conditions and choose the best #16

Closed enjoy-digital closed 9 years ago

enjoy-digital commented 9 years ago

with tx_irq_condition="empty", we have possible gaps between transfers but we are able to reduce number of irqs on large transmissions by a factor of up to tx_fifo_depth.
with tx_irq_condition="non-full", we avoid gaps (since we are able to always ensure there is something in the fifo) but for large transmissions (> to tx_fifo_depth) we then generate one interrupt per character.

An "almost-empty" solution should have both advantages without costing too much ressources. It has to be evaluated.

enjoy-digital commented 9 years ago

An optimal solution for both sync and async mode is not easy to implement, it would require moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth. For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.