Xilinx ISE 14.7 (64-Bit) HDL compiler error / clog2 function

[nanosonde]

Hello,

I was able to successfully build the blinkie project for the Spartan6 FPGA with Xilinx ISE14.7 (64-Bit) under CentOS6.5.

However, if I try to only synthesize the referenced lm32 core (lm32_top as top level) for a Virtex5, the lm32_config.v produces an ERROR: "lm32_config.v" line 187 expecting 'EOF', found 'function'

Interestingly, a similiar problem seems to appear in the synthesis log of the blinkie project, but only as a WARNING: "lm32_config.v" Line 187: Root scope declaration is not allowed in verilog 95/2K mode

I tried the same using Xilinx Vivado 2014.2 (64-Bit) for an Artix7. Here I get the message >"lm32_config.v" Line 187: Root scope declaration is not allowed in verilog 95/2K mode< again, but this time as ERROR message.

Any idea, how to fix this properly?

[nanosonde]

I have just found this: http://forums.xilinx.com/t5/Synthesis/clog2-fails-on-a-localparam/td-p/396105

and this: http://permalink.gmane.org/gmane.comp.multimedia.milkymist.devel/3042

So $clog2() system call cannot be used with "localparam" due to a bug in XST. The fix is to use a constant function in lm32_config.v.

But this fix only works for Spartan6 run of XST and NOT for a Virtex5 run of XST.

A fix from Xilinx for the "localparam" $clog() issue is to use "System Verilog" file type: http://www.xilinx.com/support/answers/57984.html

[sbourdeauducq]

Is this still a problem?

[nanosonde]

Sorry, I am not working on this anymore.