search

m-labs / misoc

The original high performance and small footprint system-on-chip based on Migen™
https://m-labs.hk
Other
306 stars 85 forks source link

DDR3 broken on some Sayma boards #63

Closed sbourdeauducq closed 6 years ago

sbourdeauducq commented 6 years ago

https://github.com/m-labs/sinara/issues/382#issuecomment-349025235

gkasprow commented 6 years ago

I have Vivado test designs that I used to verify DDR3 operation. Both memory banks tests were successful. Is there something wrong in HW? On some boards there was not mounted R205 resistor that may cause memory controller failure during initialisation. It was reported here This may cause an issue only with DDR32 controller. But Xilinx core worked fine since this sets impedance reference only on SDRAM control lines which do not need to calibrate its impedance.

enjoy-digital commented 6 years ago

@gkasprow: this is not related to HW but to our PHY. I think this is now fixed and we will close this when validated on all sayma amc.

jbqubit commented 6 years ago

I am compiling .bit from master now and will report if it works.

jbqubit commented 6 years ago

Confirmed that Memtest passes on my Sayma_AMC using .bit built from master.

sbourdeauducq commented 6 years ago

Also still works on sayma1 and sayma2 at m-labs. @enjoy-digital thanks for the rapid resolution.