SPI clock glitches on CS transitions

m-labs / misoc

The original high performance and small footprint system-on-chip based on Migen™

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SPI clock glitches on CS transitions #65

Closed jordens closed 6 years ago

jordens commented 6 years ago

Both SPIMachine.clk and SPIMachine.cs change at the same time at the start and end of a transaction. The CLK output should be registered or at the very minimum this coincident change should be removed.

https://github.com/m-labs/misoc/blob/master/misoc/cores/spi.py#L326
https://github.com/m-labs/artiq/blob/master/artiq/gateware/spi.py#L206

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