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m-labs / misoc

The original high performance and small footprint system-on-chip based on Migen™
https://m-labs.hk
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liteeth: remove dw parameterization #70

Closed sbourdeauducq closed 6 years ago

sbourdeauducq commented 6 years ago

The data path width parameter is dragged around the core but the difficult issues (e.g. unaligned SFD, unaligned CRC) are not addressed. Having a configurable data path width is not straightforward and has little practical value, all current PHYs are 1-byte wide. The parameter should be removed to reduce complexity/clutter a bit and stop giving the false impression that the core supports dw != 8.

whitequark commented 6 years ago

SaymaAMC, Kasli and KC705 MiniSoCs currently use dw=32.

sbourdeauducq commented 6 years ago

That's the dw for the PHY. That one is 8 everywhere AFAIK. Where do you see 32?