As proposed in migen #201 here's what needs to be done to remove add_sources() with an explicit list of files, which omitted files that are only referenced through include in Verilog.
In consequence, all files that are added through add_source_dir() occur in the output's top.tcl.
It also removes all verilog_include paths as the include directives only refer to files in the same source directory.
As proposed in migen #201 here's what needs to be done to remove
add_sources()with an explicit list of files, which omitted files that are only referenced throughincludein Verilog.In consequence, all files that are added through
add_source_dir()occur in the output'stop.tcl.It also removes all verilog_include paths as the
includedirectives only refer to files in the same source directory.