Tested on Red Pitaya STEMLab 125-10 and STEMLab 125-14
Author: Michel Adamic ada.mic94@gmail.com
Performance\ TDC core frequency: 350 MHz\ No. of delay line taps: 192 (configurable)\ Time resolution per channel: >11 ps\ Accuracy: <10 ppm\ DNL: -1 to +4.5 LSB\ INL: +0.5 to +8.5 LSB\ Measurement range: 47.9 ms\ Dead time: ~14 ns\ Max speed: ~70 MS/s
Included folders\ AXITDC\ TDC channel IP. Includes VHDL source files, test benches and customized Xilinx IP cores.
board\ Red Pitaya board definition files.
figs\ Various figures and schematics of the TDC design.
matlab
setup\ Files required to run the TDC system on the Red Pitaya board.
src\ Source files for creating a two-channel TDC system example project.
2-channel TDC system example project
If you don't want to run these steps and create your own FPGA bitstream, you can use the one already provided in the setup folder.
Setup on the Red Pitaya system (STEMLab 125-10 or 125-14)
TDC inputs are located on E1 extension connector pins 17 & 18 (connected to FPGA pins M14 & M15), voltage standard = LVCMOS33 (3,3 V). The TDCs are rising-edge sensitive, i.e. a timestamp is generated for each 0->1 transition.
Links\ IEEE paper: https://ieeexplore.ieee.org/abstract/document/8904850 \ My thesis (in Slovene): https://repozitorij.uni-lj.si/IzpisGradiva.php?id=117846&lang=eng \ Red Pitaya docs, schematics etc.: https://redpitaya.readthedocs.io/en/latest/