snes_dejitter is a mod board which eliminates sync jitter of NES/SNES 240p modes. Technical description and discussion is found on this thread.
Hardware
Software
Hardware
Software
NOTE: Only needed when building a custom firmware. Pre-built images can be found under output_files/ on master and nes-fix (recommended for NES/FC) branches.
Open the project file in Quartus, and run compilation
Convert MAX7000 targeted POF object file into JEDEC file suitable for 1502AS via winpof2jed.exe:
Select .pof file from previous step as input file
Select 1502AS as device
Change the following options:
Click "Run"
![pof2jed](/pics/pof2jed.png)
Convert JED to SVF via ATMISP:
Create a new device chain via File->New
Set number of devices to 1
Set device to ATF1502AS
Set JTAG instruction to "Program/Verify"
Select .jed file from previous step as JEDEC file
Click "OK"
Tick "Write SVF file" and click "Run"
![atmisp1](/pics/atmisp_chain.png)
![atmisp1](/pics/atmisp_setup.png)
The board can be flashed using any OpenOCD supported JTAG programmer that supports 3.3V-5V IO signal level (TCK, TMS and TDI are TTL inputs with 10k pull-downs). If 3.3V IO is used, JP4 (on v1.3 PCB) should be closed which clamps TDO output to 3.3V. A standalone snes_jitter board is flashed by hooking all of its 6 JTAG header pins to respective pins of the programmer/cable, and by running flash procedure specified below. After the board has been installed to NES/SNES, firmware can be subsequently updated, but in this method 5V pin of the JTAG connector MUST be left disconnected, and programming needs to be done while NES/SNES is powered on (without a game is ok). The update procedure is similar in both cases:
Board pin | Programmer pin |
---|---|
TCK | ADBUS0 |
TMS | ADBUS3 |
TDI | ADBUS1 |
TDO | ADBUS2 |
openocd -f openocd.conf
telnet localhost 4444
> svf <full_path_to_svf_file>
General descriptions on board pins are in table below. Model-specific installation instructions are added to separate subdirectories.
Board pin | Description |
---|---|
CSYNC_i | TTL C-sync signal from the console |
MCLK_EXT_i | External clock input. Used only in PAL mode, not needed in pure NTSC installations. |
CLK_SEL_i | Master clock source selection (0=internal/NTSC, 1=external/PAL). In PAL mode, MCLK and CSYNC are bypassed to output. Pin is pulled low internally, so it can be left disconnected in pure NTSC installations. Connected to PALMODE in multiregion installations. Can be forced high by bridging JP1 (pre-1.2 boards only), but must never be done if the pin is wired to console. |
MCLK_o | Clock output. An optional voltage divider (R13,R14 / JP2) can be used to reduce output level from ~4Vpp to ~3Vpp, see model-specific instructions for more details. |
CSYNC_o | C-sync output (~2.5Vpp unterminated, ~1.1Vpp into 75ohm termination) to an isolated multi-AV pin. Driver circuit is identical to SHVC-CPU-01. JP3 connects optional 330pF output capacitor that may not be present on console mainboard (not strictly needed, reduces potential noise at the price of less sharp transition time), see model-specific instructions for more details. |
Jumper | Description |
---|---|
JP1 | Forces CLK_SEL_i high. Removed on v1.2 since it was mostly for debugging purposes. |
JP2 | Enables MCLK_o voltage divider. Recommended for NES installations to ensure signal level is safe for NESRGB. |
JP3 | Connects optional 330pF output capacitor on CSYNC_o. |
JP4 | Enable TDO voltage clamp. Recommended if board is flashed with a 3.3V programmer. |