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matthijsr
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til-vhdl
A prototype toolchain for demonstrating and exploring an intermediate representation for defining components using the Tydi interface specification.
Apache License 2.0
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Vector for all bitcounts
#134
matthijsr
closed
1 year ago
0
Use vectors even for single bit data, index, strobe and last signals
#133
matthijsr
closed
1 year ago
0
Fix generic bitvector width and generic param parser on dimensionality
#132
matthijsr
closed
1 year ago
0
Parser issue: `dimensionality: d + 1,` assumes a type expression (identifier)
#131
matthijsr
closed
1 year ago
0
Generic Dimenionality -> Array is 1 bit too wide
#130
matthijsr
closed
1 year ago
0
Generic param conditions parsing
#129
matthijsr
closed
1 year ago
0
Fix the order of operations in the parser.
#128
matthijsr
closed
1 year ago
0
Order of operations in generic parameter values
#127
matthijsr
closed
1 year ago
2
Generics parser (partial)
#126
matthijsr
closed
1 year ago
0
TIL current grammar documentation and parser rewrite
#125
matthijsr
opened
1 year ago
2
Generic type decls (query system)
#124
matthijsr
closed
1 year ago
0
Generic type compat
#123
matthijsr
closed
1 year ago
0
Vhdl name restrictions
#122
matthijsr
closed
1 year ago
0
Generic type compatibility and evaluation
#121
matthijsr
opened
1 year ago
6
VHDL hierarchy issues
#120
matthijsr
closed
1 year ago
9
VHDL identifiers are case-insensitive
#119
matthijsr
closed
1 year ago
0
Dimensionality generic
#118
matthijsr
closed
1 year ago
0
Vhdl extended identifiers (quick solution)
#117
matthijsr
closed
1 year ago
0
VHDL: Consecutive underscores?
#116
matthijsr
closed
1 year ago
2
Include optional (is) and (second component_name) for component decla…
#115
matthijsr
closed
1 year ago
0
vhdeps expects "component ... is" syntax
#114
matthijsr
closed
1 year ago
1
Generic parameters
#113
matthijsr
closed
1 year ago
0
Initial Grammar for generics in TIL
#112
matthijsr
closed
1 year ago
6
Add support for mod expr in vhdl gen
#111
matthijsr
closed
1 year ago
0
Vhdl parameter mapping
#110
matthijsr
closed
1 year ago
0
Add support for generic mappings in VHDL generation
#109
matthijsr
closed
1 year ago
0
Arbitrary propagated generics
#108
matthijsr
closed
1 year ago
7
Imports between files
#107
matthijsr
opened
1 year ago
0
Other import statements
#106
matthijsr
opened
1 year ago
2
Namespace imports
#105
matthijsr
closed
1 year ago
0
Project file order should be irrelevant
#104
matthijsr
opened
1 year ago
0
Spans should account for different files
#103
matthijsr
opened
1 year ago
0
Support for "imports" between Namespaces
#102
matthijsr
closed
1 year ago
1
Salsa depends on Inputs being changed in order to update queries. Usi…
#101
matthijsr
closed
1 year ago
0
Probably shouldn't use Arc<Mutex> for Project
#100
matthijsr
closed
1 year ago
0
Support for "Projects"
#99
matthijsr
closed
1 year ago
0
Annotations
#98
matthijsr
opened
2 years ago
0
Iccad demo
#97
matthijsr
closed
2 years ago
0
Clock domains
#96
matthijsr
closed
2 years ago
0
Loc evaluation
#95
matthijsr
closed
2 years ago
0
Creating "arrays" of instances.
#94
matthijsr
opened
2 years ago
1
Vhdl physical signals
#93
matthijsr
closed
2 years ago
0
Processes and sequential statements
#92
matthijsr
closed
2 years ago
0
Remove indexmap imports where unused
#91
matthijsr
closed
2 years ago
0
Vhdl stream component
#90
matthijsr
closed
2 years ago
0
Replace IndexMap and Fields (especially Fields) with InsertionOrderedMap where possible
#89
matthijsr
closed
2 years ago
2
VHDL back-end does not account for Streams being reversed
#88
matthijsr
closed
2 years ago
1
Fix type reference split streams
#87
matthijsr
closed
2 years ago
0
Signaling trait
#86
matthijsr
closed
2 years ago
0
Implement PhysicalSignals trait in VHDL back-end
#85
matthijsr
closed
2 years ago
0
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