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mbuesch
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crcgen
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
https://bues.ch/h/crcgen
GNU General Public License v2.0
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corrected generation of MyHDL code: previous code would convert but not simulate
#3
josyb
closed
1 year ago
2
Incorrect generated MyHDL code
#2
josyb
closed
1 year ago
4
wider data input - feature request
#1
s3bs
closed
3 years ago
11