merledu / nucleusrv

NucleusRV - A 32-bit 5 staged pipelined risc-v core.
GNU General Public License v3.0
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cpu fpga riscv

NucleusRV

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A chisel based riscv 5-stage pipelined cpu design, implementing 32-bit version of the ISA (incomplete).

Dependencies

Build Instructions

Building with SBT

Run this command is SBT shell

testOnly nucleusrv.components.TopTest -- -DwriteVcd=1 -DprogramFile=/path/to/instructions/hex

Running Compliance Tests

Building C Programs