On video decode sheet, XECY is a DR_LATCH, not D_LATCH_A. Its data input comes from D7, not XEBE. But its /RESET input comes from XEBE. Enable input should be WARU, not XUCA. XUCA is connected to its /ENA input, so XUCA is just a COMP CLOCK. This is also wrong in Furrtek's schematic. It is correct that Q output is in use and /Q is NC.
On video decode sheet, XECY is a DR_LATCH, not D_LATCH_A. Its data input comes from D7, not XEBE. But its /RESET input comes from XEBE. Enable input should be WARU, not XUCA. XUCA is connected to its /ENA input, so XUCA is just a COMP CLOCK. This is also wrong in Furrtek's schematic. It is correct that Q output is in use and /Q is NC.