msinger / dmg-schematics

Reverse engineered schematics of the Game Boy's DMG-CPU B chip
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asic chip dmg-001 dmg-cpu electronics game-boy gameboy kicad-schematics nintendo reverse-engineering schematics

Game Boy DMG CPU Schematics

Contains reverse engineered schematics of the Game Boy DMG-CPU B chip.

The schematics in this repository are derived from the schematics in furrtek/DMG-CPU-Inside (CC-BY-SA 4.0 Furrtek).

PDF Export

Most recent PDF export can be found here, or in the release section on github.

Files in this repo

File(s) Description
./dmg_cpu_b/dmg_cpu_b.kicad_pro KiCad project file for the schematics of the chip.
./dmg_cpu_b/*.kicad_sch KiCad schematic sheets.
./dmg_cpu_b/lib/DMG_CPU_Cells.kicad_sym KiCad library with symbols for all the logic cells in the chip.
./dmg_cpu_b/overlay/dmg-cpu-b_overlay.svg Modified version of Furrtek's overlay for the chip's die shot.
./dmg_cells/dmg-cpu.jelib Electric VLSI cell library containing layouts of the cells used in the chip.
./netlist/*.nl Text files containing all cells and wires, and their connections and coordinates.

Overlay SVG

The overlay SVG image contains the contours of the cells in the die shot and highlights all the wires connecting the cells. Also the cells are labeled with the same names they have in the schematics.

We took the overlay from Furrtek and modified it to keep it in sync with the fixed schematics.

To open the overlay with a SVG viewer/editor (like Inkscape) you need to download the die shots and place them into the same directory where the overlay file is. The die shots can be downloaded from here and here.

Electric VLSI Library

The Electric VLSI library contains layouts and schematics for the standard cells used in the chip.

Screenshots of these layouts can be seen in the cell reference documentation here.

Netlist

The files in the netlist folder contain definitions for all cells and wires of the chip. They can be parsed by the nlconv tool. This tool is currently capable of converting the netlists into the following products:

It is planned to add the functionality to generate HDL code for simulation from the same files.