Closed tclemens closed 1 year ago
Thank you, I think you are right. Seems like we have overlooked this. If it raises bit 1 of the MODE[1:0] field in the STAT register, then it must be high during MODE2, not MODE1. I will check simulation results once more just to make sure, and then fix it.
@msinger , I can make the changes if you like.
Hi @rgalland, thanks, I'm already done. Just about to push. :)
@msinger , man! you were fast.
Let's hope I didn't miss something.
No, you haven't it seems fine. We could almost change INT_VBL to MODE1, INT_HBL to MODE2 and INT_VBL_BUF to INT_VBL.
Changing INT_VBL_BUF to INT_VBL would clean up FF0F INT (page 10). This was bothering me for a while that this is the only interrupt that hat a _BUF in its name.
Oh, careful. :) You mean, INT_HBL to MODE0.
Yes, that's what I meant.
It's source is
OAM_PARSING && !DMA_RUN
. It's also a component ofSTAT[1]
which should only be set in modes 2 and 3.