Preparation of gateware for the instantiation of RISC-V SoCs

[cairo-caplan]

• Conversion of EDF (Quartus schematics files) to VHDL.
• Implying also on the substitution of Altera Mux for VHDL constructions.
• Creation of a new block called soc_wrapper to allow the substitution of the Nios 2 system for other Systems on Chip.
• Creation of a SoC using the Orca, a RISC-V CPU, for now on qsys.
• Each SoC shall be mapped into differents HDL libraries to avoid conflicts.
• Download of the codebase for Pulpino and Mor1kx.

The system on chip options are made available on src/riscv/