The DNN+NeuroSim framework was developed by Prof. Shimeng Yu's group (Georgia Institute of Technology). The model is made publicly available on a non-commercial basis. Copyright of the model is maintained by the developers, and the model is distributed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International Public License
:star2: This is the released version 1.4 (August 1, 2023) for the tool, and this version has improved following inference engine estimation:
The following is a list of the supported nodes with key features:
130nm Same as V1.3 (PTM Model)
90nm Same as V1.3 (PTM Model)
65nm Same as V1.3 (PTM Model)
45nm Same as V1.3 (PTM Model)
32nm Same as V1.3 (PTM Model)
22nm Same as V1.3 (PTM Model)
14nm FinFET, Fin number=4 (per each NMOS/PMOS)
10nm FinFET, Fin number=3 (per each NMOS/PMOS)
7nm FinFET, Fin number=2 (per each NMOS/PMOS)
5nm FinFET, Fin number=2 (per each NMOS/PMOS)
3nm FinFET, Fin number=2 (per each NMOS/PMOS)
2nm Nanosheet (GAA), Nanosheet number=3 (per each NMOS/PMOS), Backside power rail
1nm Nanosheet (GAA), Nanosheet number=4 (per each NMOS/PMOS), Backside power rail, Dielectric wall separation, CFET design for SRAM
modify the "technnode" parameter (line 127 in Param.cpp) to match the desired case
For example technnode = 22 corresponds to a technode of 22nm and technnode = 14 corresponds to 14nm.
For additional details about the device parameters used in NeuroSim, refer to section 7 of the V1.4 manual.
Specify the parameter "parallelRead" when running the python wrapper.
Partial parallel mode will be enabled in both the python wrapper and C++ code.
--parallelRead N
Where N is the desired number of rows activated in parallel and N <= sub-array size.
globalBusType = false; // false: X-Y Bus // true: H-Tree
We recommend using anaconda package manager to install PyTorch.
This version supports the recently released PyTorch 2.0
We have currently tested the following operating systems and drivers:
(1) Red Hat 8.8 (Ootpa) gcc: v8.5.0 glibc: v2.28 NVIDIA Driver Version: 535.54.03 CUDA Version: 12.2
(2) Ubuntu 20.04 gcc: v9.4.0 glibc: v2.31 NVIDIA Driver Version: 525.60.13 CUDA Version: 12.0
git clone https://github.com/neurosim/DNN_NeuroSim_V1.4.git
cd DNN_NeuroSim_V1.4
conda create --name neurosim
conda activate neurosim
conda install pytorch torchvision torchaudio pytorch-cuda=11.7 -c pytorch -c nvidia
1. VGG8 on cifar10
8-bit "WAGE" mode pretrained model is uploaded to './log/VGG8.pth'
2. DenseNet40 on cifar10
8-bit "WAGE" mode pretrained model is uploaded to './log/DenseNet40.pth'
3. ResNet18 on imagenet
"FP" mode pretrained model is loaded from 'https://download.pytorch.org/models/resnet18-5c106cde.pth'
cd Inference_pytorch/NeuroSIM
make
cd ..
python inference.py --dataset cifar10 --model VGG8 --mode WAGE --inference 1 --cellBit 1 --subArray 128 --parallelRead 64
python inference.py --dataset cifar10 --model DenseNet40 --mode WAGE --inference 1 --cellBit 2 --ADCprecision 6
python inference.py --dataset imagenet --model ResNet18 --mode FP --inference 1 --onoffratio 100
_For estimation of on-chip training accelerators, please visit released V2.1 DNN+NeuroSim V2.1_
NOTE: the on-chip training framework has not yet been updated to support the features released in this version (DNN+NeuroSim V1.4).
We plan to support the technology scaling to 1nm, partial parallel mode and the XY bus in a future update.
In Pytorch/Tensorflow wrapper, users are able to define network structures, precision of synaptic weight and neural activation. With the integrated NeuroSim which takes real traces from wrapper, the framework can support hierarchical organization from device level to circuit level, to chip level and to algorithm level, enabling instruction-accurate evaluation on both accuracy and hardware performance of inference.
Developers: Junmo Lee :two_men_holding_hands: James Read :couple: Anni Lu :two_women_holding_hands: Xiaochen Peng :two_women_holding_hands: Shanshi Huang.
This research is supported by NSF CAREER award, NSF/SRC E2CDA program, the ASCENT center (SRC/DARPA JUMP 1.0) and the PRISM and CHIMES centers (SRC/DARPA JUMP 2.0).
If you use the tool or adapt the tool in your work or publication, you are required to cite the following reference:
X. Peng, S. Huang, Y. Luo, X. Sun and S. Yu, ※DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies, § IEEE International Electron Devices Meeting (IEDM), 2019.
If you have logistic questions or comments on the model, please contact :man: Prof. Shimeng Yu, and if you have technical questions or comments, please contact :man: Junmo Lee or :man: James Read or :woman: Anni Lu.
Documents/DNN NeuroSim V1.4 Manual.pdf
For additional details on the usage of this tool, please refer to the manual.