I am writing to need support regarding an issue I am encountering with the frequency output of a sine wave generated using a simple sine wave generator model in MATLAB, which I have implemented on an NI PXI 7868R FPGA card with PXIe-8862 8 core Embedded Controller.
While the amplitude of the sine wave is accurately represented, I am experiencing a significant discrepancy in the frequency. Specifically, when a frequency of 60 Hz is set in VeriStand 2024 Q3, the output frequency measured is approximately 281.50 Hz From NI PXIe 7868R FPGA.
I used MATLAB version 2023B to create the Bitfile for this implementation. To facilitate a thorough understanding of the issue, I have attached my Simulink model for your review. I would appreciate your expert guidance on resolving this frequency mismatch.
Thank you for your attention to this matter. I look forward to your response.
Response:
We see that you have set the Target clock to 1MHz. This is not synthesizable on our FPGA, HDL coder will then default to using the nearest available frequency that happens to be 4.69MHz. You should see a warning message in step 1.4 for this.
Since you ended up clocking your circuit at 4.69 times the desired clock, you got a frequency that is 4.69 times the desired frequency(281.5/60=4.69).
I would suggest setting a clock that is available on the target, say 10MHz or 40MHz and scale your model accordingly.
Question:
I am writing to need support regarding an issue I am encountering with the frequency output of a sine wave generated using a simple sine wave generator model in MATLAB, which I have implemented on an NI PXI 7868R FPGA card with PXIe-8862 8 core Embedded Controller.
While the amplitude of the sine wave is accurately represented, I am experiencing a significant discrepancy in the frequency. Specifically, when a frequency of 60 Hz is set in VeriStand 2024 Q3, the output frequency measured is approximately 281.50 Hz From NI PXIe 7868R FPGA.
I used MATLAB version 2023B to create the Bitfile for this implementation. To facilitate a thorough understanding of the issue, I have attached my Simulink model for your review. I would appreciate your expert guidance on resolving this frequency mismatch.
Thank you for your attention to this matter. I look forward to your response.
Response:
We see that you have set the Target clock to 1MHz. This is not synthesizable on our FPGA, HDL coder will then default to using the nearest available frequency that happens to be 4.69MHz. You should see a warning message in step 1.4 for this.
Since you ended up clocking your circuit at 4.69 times the desired clock, you got a frequency that is 4.69 times the desired frequency(281.5/60=4.69).
I would suggest setting a clock that is available on the target, say 10MHz or 40MHz and scale your model accordingly.