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FPGA
该项目适用于中山大学(Sun Yat-sen University)数字集成电路前端设计与高层次综合 Front-end Design of Digital Integrated Circuits and High-level Synthesis
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finish lib of DengFOC
#22
nightt5879
closed
1 week ago
0
Feature/hls
#21
nightt5879
closed
1 week ago
0
Feature/hls
#20
nightt5879
closed
3 weeks ago
0
add the source
#19
nightt5879
closed
3 weeks ago
0
Feature/the different version hls
#18
nightt5879
closed
3 weeks ago
0
finish lab1 PDF
#17
nightt5879
closed
3 weeks ago
0
Feature/hls
#16
nightt5879
closed
1 month ago
0
finish lab4
#15
nightt5879
closed
1 month ago
0
retry lab4
#14
nightt5879
closed
1 month ago
0
Feature/zed board
#13
nightt5879
closed
1 month ago
0
finish lab6
#12
nightt5879
closed
1 month ago
0
fix the lab2 bug
#11
nightt5879
closed
1 month ago
0
add the zedboard datasheet
#10
nightt5879
closed
1 month ago
0
typo
#9
nightt5879
closed
1 month ago
0
finish lab5
#8
nightt5879
closed
1 month ago
0
finish lab3
#7
nightt5879
closed
1 month ago
0
finish lab1 & lab2
#6
nightt5879
closed
1 month ago
0
Try/uart sample
#5
nightt5879
closed
1 month ago
0
bitstrem can't use
#4
nightt5879
closed
1 month ago
0
can load bitstream
#3
nightt5879
closed
1 month ago
0
fail to do
#2
nightt5879
closed
1 month ago
0
some questions
#1
caiyilian
opened
1 month ago
6